In many digital communication systems, the choice of various clocking frequencies is critical to the performance of the overall system. Typically a crystal oscillator is used for generating a master clock. A crystal oscillator is used because of its high precision and low frequency drift versus temperature. To generate multiple clock frequencies, some systems use two or more crystal oscillators. This adds additional size and cost to the system, which is highly undesirable for wireless communication systems such as cellular telephony.
Other systems use various clock generation techniques in order to achieve the proper multiple clock frequencies. One of these techniques is to use a binary rate multiplier (BRM) to generate a ratio of the master clock frequency from which all other clock frequencies can be generated. A clock is generated with a BRM by gating off certain clock pulses of the master clock in order to achieve the correct ratio for the generated clock. Thus a BRM generated subclock is a time average version of the target subclock frequency.
FIG. 1 is a timing diagram example of the generation of a BRM clock. The BRM generated clock is created using a 32/35 ratio to produce a 7.68 MHz clock from an 8.4 MHz clock reference. Signal 100 represents a periodic 8.4 MHz clock, and signal 102 is a clock off signal to gate off every 12th, 24th, and 35th rising edge of the signal 100 periodic clock. Signal 104 represents the aperiodic 7.68 MHz, BRM generated clock. The resulting 7.68 MHz clock is aperiodic because every 11th, 23rd, and 34th pulses are one additional master clock period wide. In addition, any subclocks generated from this BRM master clock will also be aperiodic in nature.
In a communication system employing digital demodulation, a sigma-delta digital-to-analog converter (DAC) can be used to generate an analog representation of the digital signal. The output of a sigma-delta DAC is a 1-bit oversampled, time averaged representation of a digital signal with in-band noise that is inversely related to the oversampling ratio (OSR). The OSR is defined to be the ratio of the oversampling frequency to the sampling frequency. For a first order sigma-delta DAC, each doubling of the OSR reduces the signal band noise by 9 dB. Because the output of a sigma-delta DAC is a time averaged representation of a digital signal, the use of an aperiodic sampling frequency greatly degrades the quality of the signal that is being output.
The signal degradation occurs because, in order to reconstruct the analog signal, a continuous stream of pulses with equal magnitude are generated by the sigma-delta DAC. For example, a binary 1 output is mapped to a +1 pulse and a binary 0 is mapped to a -1 pulse. The pulses are then time-averaged (low-pass filtered) to produce the reconstructed analog signal. However, for the signal to be properly reconstructed, each pulse must be of equal area. A BRM generated aperiodic clock that drives a sigma-delta DAC does not have equal area pulses.
There is a need for a sigma-delta demodulator that can demodulate data generated by an aperiodic clock. Further, the sigma-delta demodulator must not substantially degrade noise and distortion performance beyond that which would otherwise be obtained by driving the sigma-delta demodulator with periodic clock generated data. Such a demodulator would reduce circuit complexity, reduce the number of crystal oscillators needed for a communication system, maintain proper communication system performance, and reduce the cost of the communication system.